1. Field of the Invention
The present invention relates generally to semiconductor devices. More particularly, the present invention relates to semiconductor memory arrays.
2. Background Art
As known in the art, memory arrays include bit lines, sense amps, word lines, and memory cells. Examples of memory cells include static random-access memory (SRAM) cells, dynamic random-access memory (DRAM) cells, read-only memory (ROM) cells, and the like. In order to satisfy International Technology Roadmap for Semiconductors (ITRS) targets regarding area occupied by a memory array, process technologies continue to shrink. For example, ITRS targets aim for the area to be reduced by 50% per generation for SRAM-based memory arrays. While many benefits accrue from memory arrays occupying a smaller area, various challenges are also introduced as areas shrink that can increase layout area and cost of memory arrays.
As one example, shrinking memory arrays have resulted in a narrowing of word lines for memory arrays thereby increasing sheet resistance. Furthermore, overall cross-sectional area of the word lines has decreased, thereby increasing current density and impairing electromigration in the word lines. Moreover, due to increased density of memory arrays and larger number of memory cells, capacitive loading on word lines has also significantly increased. As a result, the word lines have increased resistive and capacitive loading, resulting in a high resistive-capacitive (RC) delay that decreases performance of the memory array. Splitting each of the word lines into two segments and inserting a buffer between the two segments to rebuffer a signal from a word line driver may address some of these issues. However, the buffer would introduce delay to the signal and would increase layout area. Furthermore, memory arrays have shrunk to a point where design choices are limited. For example, certain spacings are required to avoid excessive multi-bit upsets in memory cells, which result in an unacceptable soft error rate (SER).
Thus, there is need in the art for memory arrays that can overcome the drawbacks and deficiencies in the art, such as those mentioned above.